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Overview
| Comment: | On any rollback, immediately interrupt all running statements on the same database connection. This is a partial fix for ticket [f777251dc7]. |
|---|---|
| Downloads: | Tarball | ZIP archive |
| Timelines: | family | ancestors | experimental |
| Files: | files | file ages | folders |
| SHA1: |
c304b44caebc0666fdf19b3ff880f689 |
| User & Date: | drh 2009-10-15 19:45:50.000 |
| Original Comment: | On any rollback, immediately interrupt all running statements on the same database connection. This is a partial fix for ticket [f777251dc7]. |
Context
|
2009-10-15
| ||
| 19:45 | On any rollback, immediately interrupt all running statements on the same database connection. This is a partial fix for ticket [f777251dc7]. (Closed-Leaf check-in: c304b44cae user: drh tags: experimental) | |
| 18:35 | Add the experimental sqlite3_reoptimize() API. (check-in: 9bd6f3d886 user: dan tags: experimental) | |
Changes
Changes to src/main.c.
| ︙ | ︙ | |||
721 722 723 724 725 726 727 728 729 730 731 732 733 734 |
}
sqlite3BtreeRollback(db->aDb[i].pBt);
db->aDb[i].inTrans = 0;
}
}
sqlite3VtabRollback(db);
sqlite3EndBenignMalloc();
if( db->flags&SQLITE_InternChanges ){
sqlite3ExpirePreparedStatements(db);
sqlite3ResetInternalSchema(db, 0);
}
/* Any deferred constraint violations have now been resolved. */
| > | 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 |
}
sqlite3BtreeRollback(db->aDb[i].pBt);
db->aDb[i].inTrans = 0;
}
}
sqlite3VtabRollback(db);
sqlite3EndBenignMalloc();
sqlite3_interrupt(db);
if( db->flags&SQLITE_InternChanges ){
sqlite3ExpirePreparedStatements(db);
sqlite3ResetInternalSchema(db, 0);
}
/* Any deferred constraint violations have now been resolved. */
|
| ︙ | ︙ |
Changes to src/vdbe.c.
| ︙ | ︙ | |||
608 609 610 611 612 613 614 615 616 617 618 619 620 621 |
p->trace = stdout;
}
sqlite3EndBenignMalloc();
#endif
for(pc=p->pc; rc==SQLITE_OK; pc++){
assert( pc>=0 && pc<p->nOp );
if( db->mallocFailed ) goto no_mem;
#ifdef VDBE_PROFILE
origPc = pc;
start = sqlite3Hwtime();
#endif
pOp = &p->aOp[pc];
/* Only allow tracing if SQLITE_DEBUG is defined.
| > | 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 |
p->trace = stdout;
}
sqlite3EndBenignMalloc();
#endif
for(pc=p->pc; rc==SQLITE_OK; pc++){
assert( pc>=0 && pc<p->nOp );
if( db->mallocFailed ) goto no_mem;
CHECK_FOR_INTERRUPT;
#ifdef VDBE_PROFILE
origPc = pc;
start = sqlite3Hwtime();
#endif
pOp = &p->aOp[pc];
/* Only allow tracing if SQLITE_DEBUG is defined.
|
| ︙ | ︙ | |||
664 665 666 667 668 669 670 671 672 673 674 675 676 677 |
prc =db->xProgress(db->pProgressArg);
if( sqlite3SafetyOn(db) ) goto abort_due_to_misuse;
if( prc!=0 ){
rc = SQLITE_INTERRUPT;
goto vdbe_error_halt;
}
nProgressOps = 0;
}
nProgressOps++;
}
#endif
/* Do common setup processing for any opcode that is marked
** with the "out2-prerelease" tag. Such opcodes have a single
| > | 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 |
prc =db->xProgress(db->pProgressArg);
if( sqlite3SafetyOn(db) ) goto abort_due_to_misuse;
if( prc!=0 ){
rc = SQLITE_INTERRUPT;
goto vdbe_error_halt;
}
nProgressOps = 0;
CHECK_FOR_INTERRUPT;
}
nProgressOps++;
}
#endif
/* Do common setup processing for any opcode that is marked
** with the "out2-prerelease" tag. Such opcodes have a single
|
| ︙ | ︙ | |||
774 775 776 777 778 779 780 |
**
** An unconditional jump to address P2.
** The next instruction executed will be
** the one at index P2 from the beginning of
** the program.
*/
case OP_Goto: { /* jump */
| < | 776 777 778 779 780 781 782 783 784 785 786 787 788 789 |
**
** An unconditional jump to address P2.
** The next instruction executed will be
** the one at index P2 from the beginning of
** the program.
*/
case OP_Goto: { /* jump */
pc = pOp->p2 - 1;
break;
}
/* Opcode: Gosub P1 P2 * * *
**
** Write the current address onto register P1
|
| ︙ | ︙ | |||
4148 4149 4150 4151 4152 4153 4154 |
*/
case OP_Prev: /* jump */
case OP_Next: { /* jump */
VdbeCursor *pC;
BtCursor *pCrsr;
int res;
| < | 4149 4150 4151 4152 4153 4154 4155 4156 4157 4158 4159 4160 4161 4162 |
*/
case OP_Prev: /* jump */
case OP_Next: { /* jump */
VdbeCursor *pC;
BtCursor *pCrsr;
int res;
assert( pOp->p1>=0 && pOp->p1<p->nCursor );
pC = p->apCsr[pOp->p1];
if( pC==0 ){
break; /* See ticket #2273 */
}
pCrsr = pC->pCursor;
if( pCrsr==0 ){
|
| ︙ | ︙ | |||
4697 4698 4699 4700 4701 4702 4703 |
** register P3. Or, if boolean index P1 is initially empty, leave P3
** unchanged and jump to instruction P2.
*/
case OP_RowSetRead: { /* jump, out3 */
Mem *pIdx;
i64 val;
assert( pOp->p1>0 && pOp->p1<=p->nMem );
| < | 4697 4698 4699 4700 4701 4702 4703 4704 4705 4706 4707 4708 4709 4710 |
** register P3. Or, if boolean index P1 is initially empty, leave P3
** unchanged and jump to instruction P2.
*/
case OP_RowSetRead: { /* jump, out3 */
Mem *pIdx;
i64 val;
assert( pOp->p1>0 && pOp->p1<=p->nMem );
pIdx = &p->aMem[pOp->p1];
pOut = &p->aMem[pOp->p3];
if( (pIdx->flags & MEM_RowSet)==0
|| sqlite3RowSetNext(pIdx->u.pRowSet, &val)==0
){
/* The boolean index is empty */
sqlite3VdbeMemSetNull(pIdx);
|
| ︙ | ︙ |