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Check-in [8194dd2814]
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Overview
Comment:Previous check-in was not correct. This is a better fix for the OP_Once problem of ticket [06796225f59c057cd120f1].
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SHA3-256: 8194dd2814b0b3f8cffbcb16306f55aabf1c1508b9d27fa806f92f0e6ecd7631
User & Date: drh 2017-03-24 18:38:41.822
Context
2017-03-24
19:45
Fix a harmless compiler warning in the JSON1 extension. (check-in: c2c3dd8453 user: drh tags: trunk)
18:38
Previous check-in was not correct. This is a better fix for the OP_Once problem of ticket [06796225f59c057cd120f1]. (check-in: 8194dd2814 user: drh tags: trunk)
17:59
Fix the OP_Once opcode so that it works correctly for recursive triggers. Ticket [06796225f59c057cd120f1]. (check-in: 2556014514 user: drh tags: trunk)
Changes
Unified Diff Ignore Whitespace Patch
Changes to src/vdbe.c.
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case OP_Once: {             /* jump */
  u32 iAddr;                /* Address of this instruction */
  assert( p->aOp[0].opcode==OP_Init );
  if( p->pFrame ){
    iAddr = (int)(pOp - p->aOp);
    if( (p->pFrame->aOnce[iAddr/8] & (1<<(iAddr & 7)))!=0 ){
      VdbeBranchTaken(1, 2);
      p->pFrame->aOnce[iAddr/8] |= 1<<(iAddr & 7);
      goto jump_to_p2;
    }

  }else{
    if( p->aOp[0].p1==pOp->p1 ){
      VdbeBranchTaken(1, 2);
      goto jump_to_p2;
    }
  }
  VdbeBranchTaken(0, 2);







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case OP_Once: {             /* jump */
  u32 iAddr;                /* Address of this instruction */
  assert( p->aOp[0].opcode==OP_Init );
  if( p->pFrame ){
    iAddr = (int)(pOp - p->aOp);
    if( (p->pFrame->aOnce[iAddr/8] & (1<<(iAddr & 7)))!=0 ){
      VdbeBranchTaken(1, 2);

      goto jump_to_p2;
    }
    p->pFrame->aOnce[iAddr/8] |= 1<<(iAddr & 7);
  }else{
    if( p->aOp[0].p1==pOp->p1 ){
      VdbeBranchTaken(1, 2);
      goto jump_to_p2;
    }
  }
  VdbeBranchTaken(0, 2);
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  p->nChange = 0;
  p->pFrame = pFrame;
  p->aMem = aMem = VdbeFrameMem(pFrame);
  p->nMem = pFrame->nChildMem;
  p->nCursor = (u16)pFrame->nChildCsr;
  p->apCsr = (VdbeCursor **)&aMem[p->nMem];
  pFrame->aOnce = (u8*)&p->apCsr[pProgram->nCsr];

  p->aOp = aOp = pProgram->aOp;
  p->nOp = pProgram->nOp;
#ifdef SQLITE_ENABLE_STMT_SCANSTATUS
  p->anExec = 0;
#endif
  pOp = &aOp[-1];








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  p->nChange = 0;
  p->pFrame = pFrame;
  p->aMem = aMem = VdbeFrameMem(pFrame);
  p->nMem = pFrame->nChildMem;
  p->nCursor = (u16)pFrame->nChildCsr;
  p->apCsr = (VdbeCursor **)&aMem[p->nMem];
  pFrame->aOnce = (u8*)&p->apCsr[pProgram->nCsr];
  memset(pFrame->aOnce, 0, (pProgram->nOp + 7)/8);
  p->aOp = aOp = pProgram->aOp;
  p->nOp = pProgram->nOp;
#ifdef SQLITE_ENABLE_STMT_SCANSTATUS
  p->anExec = 0;
#endif
  pOp = &aOp[-1];

Changes to test/triggerG.test.
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  INSERT INTO t3 VALUES(2);
  SELECT c FROM t3 ORDER BY c;;
} {2 3 4 5}
do_execsql_test 110 {
  SELECT b FROM t2 ORDER BY b;
} {202 203 302 303 402 403 502 503}



















finish_test







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  INSERT INTO t3 VALUES(2);
  SELECT c FROM t3 ORDER BY c;;
} {2 3 4 5}
do_execsql_test 110 {
  SELECT b FROM t2 ORDER BY b;
} {202 203 302 303 402 403 502 503}

do_execsql_test 200 {
  DELETE FROM t1;
  INSERT INTO t1(a) VALUES(0),(2),(3),(8),(9);
  DELETE FROM t2;
  DELETE FROM t3;
  DROP TRIGGER tr;
  CREATE TRIGGER tr AFTER INSERT ON t3 BEGIN
    INSERT INTO t3 SELECT new.c+1 WHERE new.c<5;
    INSERT INTO t2 SELECT new.c*10000+xx.a*100+yy.a
                     FROM t1 AS xx, t1 AS yy
                    WHERE xx.a IN (1,2,3,4)
                      AND yy.a IN (2,3,4,5);
  END;

  INSERT INTO t3 VALUES(2);
  SELECT b FROM t2 ORDER BY b;
} {20202 20203 20302 20303 30202 30203 30302 30303 40202 40203 40302 40303 50202 50203 50302 50303}

finish_test